Many integrated circuits have signal lanes that support transmission and/or receipt of data signals. Those signal lanes can include circuitry (e.g., serializer/deserializer, or SERDES, circuits) to prepare bit data for transmission and/or to recover bit data after receipt. Noise sources and other non-idealities can produce random jitter (RJ) on clocking signals (e.g., on the output of the phase-locked loop (PLL)). For high-speed SERDES links, RJ on the PLL output can appreciably affect the link performance. Typically, the RJ seen in a SERDES link is directly affected by loop parameters (e.g., charge pump current, voltage controlled oscillator gain, supply voltage, etc.), and the performance can vary appreciably due to different process characteristics, voltages, temperatures, and/or other characteristics, even with the same loop parameter settings. Performance impacts can be further exacerbated when a single chip contains many lanes, each adding to process variations and ultimately degrading yield. For example, some modern processors include hundreds of lanes with tens of PLLs. Conventional approaches to addressing RJ in high-speed SERDES links tend to focus on designing high-accuracy PLLs across different corners, but such approaches can involve tremendous effort and can become impractical as the link speed and number of lanes increase.